Design the 4-to-1 Multiplexer Using if and Else Statements

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

• Forums
• Digital Design and Embedded Programming
• ASIC Design Methodologies and Tools (Digital)

You are using an out of date browser. It may not display this or other websites correctly.
You should upgrade or use an alternative browser.

code for 4:1 mux in verilog?tell the difference

• Thread starter abhineet22
• Start date May 19, 2005

Status

Not open for further replies.

• #1

Joined

Jan 25, 2005

Messages

105

Helped

0

Reputation

0

Reaction score

0

Trophy points

1,296

Location

bangalore

Activity points

1,017

verilog 4:1 mux

. Design a 4:1 mux in Verilog.

Multiple styles of coding. e.g.
Using if-else statements
if(sel_1 == 0 && sel_0 == 0) output = I0;
else if(sel_1 == 0 && sel_0 == 1) output = I1;
else if(sel_1 == 1 && sel_0 == 0) output = I2;
else if(sel_1 == 1 && sel_0 == 1) output = I3;

Using case statement

case ({sel_1, sel_0})
00 : output = I0;
01 : output = I1;
10 : output = I2;
11 : output = I3;
default : output = I0;
endcase

1What are the advantages / disadvantages of each coding style shown above?
2How Synthesis tool will give result for above codes?
3What happens if default statement is removed in case statement?
4What happens if combination 11 and default statement is removed?

• #2

Joined

Aug 1, 2002

Messages

21

Helped

2

Reputation

4

Reaction score

1

Trophy points

1,283

Activity points

114

verilog mux

1. one (if) has priority the other(case) has no
2. case have full/parallel concept
3. no impact to remove the default since the case is full case
4. possible mismatch in gatelevel and rtl simulation.

• #3

Joined

Dec 26, 2003

Messages

304

Helped

8

Reputation

16

Reaction score

2

Trophy points

1,298

Activity points

2,692

priority mux verilog

Hi, kxchorus,

During simulation phase, remove the default statement may cause the unknow to spread.

Good Luck

• #4

Joined

Apr 30, 2004

Messages

33

Helped

0

Reputation

0

Reaction score

0

Trophy points

1,286

Activity points

261

4:1 mux verilog

u can read synopsys sold documents about DC.

• #5

spauls

Advanced Member level 2

Joined

Dec 17, 2002

Messages

524

Helped

26

Reputation

52

Reaction score

9

Trophy points

1,298

Activity points

3,354

design a 4:1 mux in verilog

using assign is better, it will not cause sim/synt mismatch.

• #6

Joined

May 21, 2004

Messages

94

Helped

5

Reputation

10

Reaction score

2

Trophy points

1,288

Activity points

762

case verilog

If-else logic and case logic has different timing delay. Every possible condition should be outlined in combination logic block no matter if-else logic or case logic, Or else ,latch will be introduced.

• #7

Joined

Mar 28, 2005

Messages

59

Helped

3

Reputation

6

Reaction score

1

Trophy points

1,288

Activity points

1,813

4:1 verilog mux

hi,

if else can give you the priority type mux hardware while case statement will give you single mux.

with regards,
kul.

• #8

Joined

Dec 30, 2004

Messages

58

Helped

3

Reputation

6

Reaction score

3

Trophy points

1,288

Activity points

686

verilog if else simulate mux

Multiple styles of coding. e.g.
Using if-else statements
if(sel_1 == 0 && sel_0 == 0) output = I0;
else if(sel_1 == 0 && sel_0 == 1) output = I1;
else if(sel_1 == 1 && sel_0 == 0) output = I2;
else if(sel_1 == 1 && sel_0 == 1) output = I3;

Using case statement

case ({sel_1, sel_0})
00 : output = I0;
01 : output = I1;
10 : output = I2;
11 : output = I3;
default : output = I0;
endcase

1What are the advantages / disadvantages of each coding style shown above?
2How Synthesis tool will give result for above codes?
3What happens if default statement is removed in case statement?
4What happens if combination 11 and default statement is removed?

Here there is no difference between the two codes, the output is the same, as well the priority is not taken into consideration in the above logic, prioritycomes under different conditions, when the above control signals are different, what i mean to say is when one statement is used for different select signal and the other used for different select signal then priority comes under picture.

Here as u r mentioning all the the possibilities of the two signals that is 00, 01, 10, 11 then there is no difference, there is difference when u r using a full case and a parallel case

hope it is understandable

regards

• #9

Joined

Jun 10, 2005

Messages

373

Helped

8

Reputation

16

Reaction score

3

Trophy points

1,298

Activity points

4,550

4-1 mux and verilog

after DC synthesis, same result will be generated.

. Design a 4:1 mux in Verilog.

Multiple styles of coding. e.g.
Using if-else statements
if(sel_1 == 0 && sel_0 == 0) output = I0;
else if(sel_1 == 0 && sel_0 == 1) output = I1;
else if(sel_1 == 1 && sel_0 == 0) output = I2;
else if(sel_1 == 1 && sel_0 == 1) output = I3;

Using case statement

case ({sel_1, sel_0})
00 : output = I0;
01 : output = I1;
10 : output = I2;
11 : output = I3;
default : output = I0;
endcase

1What are the advantages / disadvantages of each coding style shown above?
2How Synthesis tool will give result for above codes?
3What happens if default statement is removed in case statement?
4What happens if combination 11 and default statement is removed?

• #10

Joined

Nov 4, 2012

Messages

1

Helped

0

Reputation

0

Reaction score

0

Trophy points

1,281

Location

Chennai

Activity points

1,284

module MUX_4_1(
input [3:0]i,
input [1:0]s,
output o
);
assign o= (s[0]==0)?((s[1]==0)?i[0]:i[1])(s[1]==0)?i[2]:i[3]);

endmodule

Status

Not open for further replies.

Similar threads

• Forums
• Digital Design and Embedded Programming
• ASIC Design Methodologies and Tools (Digital)

• This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
  By continuing to use this site, you are consenting to our use of cookies.

Design the 4-to-1 Multiplexer Using if and Else Statements

Source: https://www.edaboard.com/threads/code-for-4-1-mux-in-verilog-tell-the-difference.38597/

Share this post